DSC POWER 864 - REV2 Spécifications télécharger pdf (Page 178)

100

101

PIC24F16KA102 FAMILY

EQUATION 22-1: A/D CONVERSION CLOCK PERIOD

(1)

FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL

Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.

TAD = TCY • (ADCS + 1)

TAD

TCY

ADCS = – 1

CPIN

ANx

T = 0.6V

LEAKAGE

RIC ≤ 250W

Sampling

Switch

CHOLD

= DAC capacitance

VDD

= 4.4 pF (Typical)

±500 nA

Legend: CPIN

ILEAKAGE

RIC

RSS

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

various junctions

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.

RSS ≤ 5 kΩ (Typical)

6-11 pF

(Typical)

1 2 ... 173 174 175 176 177 178 179 180 181 182 183 ... 253 254

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DSC POWER 864 - REV2 Spécifications Page 178

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